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Question What is level and requirements of ESD protection during the wafer probing Process ( from wafer out of fab. to wafer is ready for back-end procedure)? If so, why? What is the max. static electricity (in volt) that is allowed in the wafer probing area? Is there a standard, an ESD hand book or an article, which could be used as a reference or standard in the wafer probing process? Please reply in detail as soon as possible and your help is highly appreciated. - Ting from Science Park of Taiwan
Answer There is no standard level requirement for ESD protection of wafer probing. This level you'd want to be protected at varies depending on the sensitivity of the devices fabricated on the wafer. The only way to determine this level of sensitivity is to test them with an ESD tester for HBM and CDM models. The ESD Association has standards for each model, but at the component and not wafer level: ESD STM5.1-1998, Human Body Model (HBM) Component Level ESD STM5.3.1-1999, Charged Device Model (CDM) Component Level.
 
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