!
REGISTER / LOGIN
SHOP
CART (
0
)
SUBSCRIBE TO OUR EMAIL LIST - Be the first to know
about exclusive deals, tips, new products & more!
Questions And Answers
#
693
List All Questions
Search
List by Category
Question
Under MIL. STD.883e 3015.7 Is there any ‘implied’ allowance to condition pins during HBM ESD zap based on ‘unique’ analog circuit functionality? Intuitively it doesn’t make sense, but there may be a practical side...any thoughts or experience? Anonymous, South Portland, Maine
Answer
I asked a colleague, Mike Hopkins from KeyTek, and his reply is no, there are no conditioning requirements for devices under the HBM testing found in either ESD Association or JEDEC standards. There is, however, a conditioning requirement in the JEDEC standard 78 for conditioning devices for Latch-up Testing.
Related Categories:
ESD Models
Simulators
If you have found this Q/A useful, please rate it based on its helpfulness.
This question has been rated:
(
0
% at
0
Ratings)